Session 28-2

A 188-size 2.1mm^2 Reconfigurable Turbo Decoder Chip with Parallel Architecture for 3GPP LTE System

 

Abstract

This paper presents a turbo decoder chip supporting all 188 block sizes in 3GPP LTE standard. The design allows 1, 2, 4, or 8 SISO decoders to concurrently process each block size, and the number of iteration can be adjusted. Moreover, a three-stage network is utilized to connect multiple memory modules and multiple SISO decoders. After fabricated in 90nm process, the 2.1mm^2 chip can achieve 129Mbps with 219mW for the 6144-bit block after 8 iterations.