Session 28-4

A 200Mbps+ 2.14nJ/b digital baseband multi processor system-on-chip for SDRs

 

Abstract

The design of an energy-efficient digital baseband multi processor system-on-chip is presented. It is implemented in 90nm CMOS technology and occupies 32mm2. This chip incorporates all digital signal processing required by the physical layer of the WiFi(802.11n), WiMax(802.16e), mobile TV and 3GPP-LTE standards. The heterogeneous architecture with hierarchical wake-up achieves 5mW idle time power, is capable of delivering a net data rate in excess of 200Mbps, and consumes 231mW during 108Mbps WLAN 2x2 MIMO Rx.