Session 5-1

A 0.6mW/Gbps, 6.4-8.0Gbps Serial Link Receiver Using
Local Injection-Locked Ring Oscillators in 90nm CMOS

 

Abstract

This paper describes a quad-channel, 6.4-8Gbps serial link receiver testchip using a global forwarded clock distribution coupled to local injection-locked ring oscillators in 90nm CMOS. Each receiver consists of a low-power linear equalizer, four offset-cancelled quantizers for 1:4 demultiplexing, and an injection-locked ring oscillator for greater than one UI of phase deskew. Measured results show a 6.4-7.2Gbps data rate with BER < 10-15 across 10cm of FR4 backplane, and 8.0Gpbs data rate with direct input. Designed in a 1.2V, 90nm CMOS process, the area of each receiver is 0.0174mm2, with a measured power efficiency of 0.6mW/Gbps.