Session 5-3

A 21-Gb/s 87-mW Transceiver with FFE/DFE/Linear Equalizer in 65-nm CMOS Technology

 

Abstract

This paper presents an ultra low-power transceiver for 20-Gb/s backplane communications. Incorporating half-rate, power-saving transmitter and full-rate, high-speed receiver with 2-stage equalization, this work achieves 21 Gb/s with BER<10^-12 over a 40-cm (16-inch) regular FR4 channel, while consuming a total power of only 87 mW from a 1.2-V supply.