Session 5-5

A Self-Calibrating Transceiver for Source Synchronous Clocking System with On-Chip TDR and Swing Level Control Scheme

 

Abstract

A transceiver chip with per-pin de-skew and read latency detection scheme utilizing on-chip TDR was implemented in 60nm DRAM process for the interface with source synchronous clock system. Without multi-phase clock, each time skew between Strobe and 16 Data was corrected within 0.028UI at 1.6-Gb/s data rate. Also, the jitter reduction of about 50% was measured with swing-level controlled voltage-mode driver in the absence of destination termination at 1.6-Gb/s.