Session 7-3

Technology portable, 0.04mm2, Ghz-rate Sigma
Delta modulators in 65nm and 45nm CMOS

 

Abstract

An area reducing design methodology is used to design three 0.04mm2, 5th order, 1-bit, Sigma Delta modulators. A 1.2V/65nm chip contains a feedback (FB) modulator sampled at 1GHz, and a 1.1V/45nm chip contains a FB and feed-forward (FF) modulator sampled at 1.5Ghz. Each modulator achieves an SNR of 60dB in 15MHz. Furthermore a method is presented, which perfectly compensates for excess phase in a Sigma Delta loop, without compromising loop stability and noise shaping.