Session 7-4

A 79dB 80MHz 8X-OSR Hybrid Delta-Sigma/Pipeline ADC

 

Abstract

A new delta-sigma modulator architecture is presented. The proposed implementation employs a pipeline ADC as the quantizer of a single-loop delta-sigma modulator and makes use of inherent delays of pipeline ADC stages to enhance overall noise shaping properties. With a 5MHz bandwidth and 80MHz clock, the measured dynamic range and SNDR of this prototype IC are 79dB and 75.4dB. The prototype chip is implemented in a 0.18É m CMOS process.