Session 11A-1

A Scalable and Highly Manufacturable Single Metal Gate
/High-k CMOS Integration for Sub-32nm Technology
for LSTP Applications

 

Abstract

This paper reports on a scalable and simple gate-first integration option for manufacturing the high-k/metal gate CMOS transistors targeting sub-32nm LSTP applications: Vt<±0.45V (at Lg=60nm) at EOT≦1.4nm, with 105x Jg reduction compared to SiO2. This scheme integrates several simplifications and improvements for the first time: single metal gate material, single channel material, dual selective LaOx / AlOx cap removal without lithographic overlay tolerances issues and optimized HfSiON for LSTP leakage targets.