Session 11A-3
Fully Depleted Extremely Thin SOI Technology Fabricated
by a Novel Integration Scheme Featuring Implant-Free,
Zero-Silicon-Loss, and Faceted Raised Source/Drain
| A novel integration scheme is presented to solve multiple issues for ETSOI technology. Source/drain and extensions are formed by an implant-free process with great reduction in series resistance. A zero-silicon-loss process is developed to minimize silicon loss, enabling sub-2nm ETSOI. A novel faceted RSD leads to 15% reduction in parasitic capacitance. Remarkable drive currents and excellent electrostatics are simultaneously achieved with gate length down to 25nm, indicating ETSOI devices suitable for 22-nm node and beyond. |