Session 3A-2

Cost-Effective 28-nm LSTP CMOS
using Gate-First Metal Gate/High-k Technology

 

Abstract

Metal gate/high-k CMOS technology for 28-nm node low power and low standby power application is demonstrated. A gate-first single metal/high-k gate stack has been employed together with leading-edge isolation, ultra-shallow junction, and stress engineering technologies. High density and high performance device is provided with least process cost increase.