Session 3A-3

Optimized Ultra-Low Thermal Budget Process Flow
for Advanced High-K / Metal Gate First CMOS
Using Laser-Annealing Technology

 

Abstract

This paper presents for the first time the successful integration of laser-only annealing in a High-K / Metal gate first process flow with functional ring oscillators. The process has been optimized to limit defect creation, reduce poly-silicon resistance and obtain good capping/High-k intermixing. EOT reduction with less eWF roll-off, excellent device scalability without performance penalty and Vth-matching improvement compared to spike have been achieved.