Session 3A-4

Impact of Area Scaling on Threshold Voltage Lowering
in La-Containing High-k/Metal Gate NMOSFETs
Fabricated on (100) and (110)Si

 

Abstract

Impact of area scaling (especially narrow channel) on Vt lowering by La incorporation in high-k gate NMOSFETs is reported for the first time. It is clarified that Vt becomes higher in narrower channel for La-containing high-k gate. Efforts are made to ascribe the strong dependence of Vt on gate width to less effectiveness of La compared to wider channel. Influence of channel orientation at STI edge is focused on to explain this phenomenon. It is presented that excellent narrow channel characteristic can be obtained using proper La-amount range and improved annealing process.