Session 4B-1

Vth Variation and Strain Control of High Ge% Thin SiGe Channels
by Millisecond Anneal Realizing High Performance pMOSFET beyond 16nm node

 

Abstract

We have studied key parameters for controlling threshold voltage (Vth) variation and strain maintenance of gate first SiGe channel pMOSFETs. By overcoming 1) Ge diffusion and 2) strain relaxation during source/drain activation, we for the first time demonstrate high Ge% (50%) SiGe channel with millisecond flash anneal. Optimizing the thermal budget with millisecond anneal keeps the Vth variation same to Si unlike RTA anneal while still having 2.8² mobility gain. We achieved high performance SiGe pMOSFETs with appropriate Vth [-0.2~-0.3V], ~1nm EOT and superior NBTI [<30mV] reliability for the integration of SiGe channel for pMOSFETs.