Session 4B-3

New Approach to Form EOT-Scalable Gate Stack
with Strontium Germanide Interlayer for High-k/Ge MISFETs

Abstract
 A new approach to form EOT-scalable high-k/Ge gate stack with a Sr germanide (SrGex) interlayer has been demonstrated to avoid drawbacks originating from thermally unstable nature of Ge oxide interlayer. Significant reduction of Jg has been observed due to the new interlayer. A promising EOT scalability is confirmed at around EOT of 1nm. A record high peak hole mobility of 481cm² /Vsec for high-k/Ge p-MISFETs has been obtained in LaAlO3 /SrGeX/Ge p-MISFETs.