Session 5B-2

Ultimate Contact Resistance Scaling Enabled
by an Accurate Contact Resistivity Extraction Methodology
for Sub-20 nm Node

 

Abstract

The S/D-to-silicide contact resistivity is accurately extracted from state-of-the-art CMOS devices based on a new extraction methodology featuring parasitic and geometric corrections. With this sensitive extrac-tion methodology and advanced S/D formation processes, low 10-8 W-cm2 CMOS contact resistivity meeting 2007 ITRS projection for sub-20 nm technologies is demonstrated. In the quest for less dominant contact resistance and therefore lower overall parasitic resistance, this work also reveals that the scaling of plug-to-spacer pitch and S/D sheet resistance becomes equally crucial as the scaling of contact resistivity.