Session 8A-1

Comprehensive Design Methodology
of Dopant Profile to Suppress Gate-LER-induced
Threshold Voltage Variability in 20nm NMOSFETs

 

Abstract

We have demonstrated for the first time that parallel extension implantation tilted along the gate width direction enables to reduce the threshold voltage fluctuation in nMOSFETs at high Vd by 15%. We have clarified by direct carrier profiling and 3D simulation that the parallel implantation makes lateral extension edge smooth. Thanks to reduced fluctuation in effective channel length, we have made it possible to stably operate 20-nm nMOSFETs.