Session 8A-2

Post-Fabrication Self-Convergence Scheme
for Suppressing Variability
in SRAM Cells and Logic Transistors

 

Abstract

A new concept for suppressing variability in SRAM cells and logic transistors is proposed. The novel method utilizes self-convergence mechanisms: Vth of transistors connected to "low" node (SRAM) and Vth of transistors with low Vth (logic) are selectively raised by applying high bias voltage to all transistors collectively after chip fabrication, resulting in lower variability in retention-noise-margin (RetNM) in SRAM and Vth in logic transistors. The concept is validated by simulation and experiments.