Session 8B-1
Sophisticated methodology
of Dummy Pattern Generation
for Suppressing Dislocation Induced contact Mis-alignment
on Flash Lamp Annealed eSiGe Wafer
| Defects-induced contact mis-alignment when combining embedded SiGe with flash lamp annealing (FLA) on high performance 40nm CMOS process has been analyzed both by experiments and novel dislocation loop dynamics simulation. Design guide lines on shape of SiGe patterns for slip free condition have been investigated and clarified. With this optimized SiGe patterns, random component of CS misalignment have been successfully reduced to lead the high SRAM yields at 40nm tech node with high performance. |