Session 8B-3

26 nm gate length CMOSFETs
with an aggressively reduced silicide position
using cluster carbon co-implantation for junction design

 

Abstract

We demonstrated 25 nm gate length CMOSFETs with an aggressively reduced silicide position down to 5 nm from the gate edge realized about one decade of order junction leakage reduction, and 10% Ion improvement for both N and PFET. Carbon cluster co-implanted raised source/drain extension (SDE) structure, that enables to enhance SDE boron concentration at the silicide interface and to reduce deep halo dosage without short channel effect degradation, is a key to achieve both low parasitic resistance and low junction leakage.