Session 9A-1

GeOI and SOI 3D Monolithic Cell integrations
for High Density Applications

 

Abstract

In this work, 3D monolithic cells have been demonstrated, featuring the first perfectly crystalline upper active layer thanks to wafer bonding. The low temperature process (<600 degree) of the top GeOI and SOI MOSFETs leads to well behaved characteristics and allows preservation of bottom FETs performance. The benefit of the decreased process temperature is highlighted by improved short channel effect control down to LG = 50nm. Both gains in density and performance have been studied with advanced design rules. Processing CMOS on each layer leads to an average 40% density improvement as compared to 2D standard layout.