Session 11-2

A -104dBc/Hz In-Band Phase Noise 3GHz All Digital PLL
with Phase Interpolation Based Hierarchical Time
to Digital Convertor

 

Abstract

An ADPLL which uses a time-to-digital convertor with <0.13rad resolution achieves LO generation at 3GHz with -104dBc/Hz in-band phase noise. The fine and stable resolution is derived by known phase interpolation circuits. It is fabricated in a 65nm CMOS process and the active area is 0.18mm2.