Session 11-4

A 2 GHz Fractional-N Digital PLL
with 1b Noise Shaping Delta-Sigma TDC

 

Abstract

A 2 GHz fractional-N digital PLL with a single delay cell, noise shaping delta-sigma TDC is implemented in a 0.13µm CMOS. With a simple structure of delta modulator followed by a charge pump integrator, a wide range TDC input is converted to delta-sigma modulated bit stream. The implemented TDC consumes 1 mA, and the DPLL shows the in-band phase noise of -107 dBc at 500 kHz offset.