Session 12-1

A 12b 3GS/s Pipeline ADC with 500mW
and 0.4 mm² in 40nm Digital CMOS

 

Abstract

A 12b 3GS/s 2-way interleaved pipeline ADC is presented. To achieve high speed, multiple internally generated power/ground rails are used with thin-oxide MOS devices. The ADC achieves a SNR of 61dB and a DNL of -0.4/+0.6LSB, consumes 500mW at 3GS/s and occupies 0.4 mm2 area in 40nm CMOS process.