Session 12-2

An 11b 300MS/s 0.24pJ/Conversion-Step Double-Sampling
Pipelined ADC with On-chip Full Digital Calibration
for all nonidealities including Memory Effects

 

Abstract

An 11b Double-Sampling Pipelined ADC with memory effect calibration is presented. The full digital calibration simplifies the analog circuit, which extends the operation speed over 300MHz. The chip is fabricated in a 40nm CMOS and occupies 0.42mm2 including the calibration logics. The ADC consumes 40mW from a 1.8V supply, and the FoM is 0.24pJ/conversion-step.