Session 12-4

A 10b 320 MS/s 40 mW Open-Loop Interpolated Pipeline ADC

 

Abstract

An open-loop interpolated pipeline ADC is proposed. Weight controlled capacitor arrays are introduced to realize an interpolation and a pipelined operation with open-loop amplifiers. The 10-bit ADC fabricated in 90nm CMOS demonstrates ENOB of 8.5b over 80MHz bandwidth (BW) and a conversion rate of 320MS/s without linearity compensation and consumes 40mW. The FoMs are 780fJ/c.-s. defined by the 80MHz BW and 390fJ/c.-s. defined by the 320 MSps conversion rate with a BW of 80MHz.