Session 12-5

A 16mW 8-bit 1-GS/s Subranging ADC in 55nm CMOS

 

Abstract

A subranging ADC was fabricated using a 55nm CMOS technology. To improve speed, subranging is executed in the digital domain by activating comparators. To save power, comparators are latches with automatic offset calibration. Operating at 1GHz sampling rate, the ADC consumes 16mW from 1.2V supplies. The measured DNL is 0.8LSB and INL is 1.2LSB. The measured SFDR and SNDR are 55dB and 43.5dB respectively. The ADC occupies active area of 0.2mm2. Its FOM is 125fJ/conversion-step.