Session 13-2

A 2.37Gb/s 284.8mW Rate-Compatible (491,3,6)
LDPC-CC Decoder

 

Abstract

In this paper, a (491, 3, 6) time-varying LDPC-CC decoder chip supporting five code-rates is implemented in 90nm CMOS technology.The decoder containing 5 processors occupies 2.24mm2 and provides twice faster decoding convergence speed.Maximum throughput 2.37Gb/s is measured under 1.2V supply with a 0.024nJ/bit/proc energy efficiency.