Session 13-3

A 1.1 GOPS/mW FPGA Chip with Hierarchical Interconnect Fabric

 

Abstract

A 2048 look-up-table FPGA with a radix-2 hierarchical interconnect network is realized in 3.94mm2 in 65-nm CMOS. It has an interconnect-to-logic area ratio of 1:1, which is a 3-4x reduction from modern FPGAs while allowing up to 100% resource utilization. As a proof of concept, it is designed with standard cells, achieving 16.4 GOPS/mm2 at 370MHz. Peak energy efficiency of 1.1 GOPS/mW is measured at 0.5V.