Session 15-3

High-PSRR All-Digital Delay Locked Loop
with Burst Update Mode and Power Noise Damping Scheme

 

Abstract

The proposed all-digital delay locked loop (DLL) eliminates power noise jitter over all frequency range by combining two methods: Burst update mode and power noise damping filter. The design is fabricated in Hynix's late 30nm DRAM process and tested with DRAM full-chip operations. The jitter of the proposed DLL was measured in a single-para ATE (Automatic Test Equipment). In 1333Mbps, the measured jitter is 34ps at VDD of 1.5V with the operation current of 1.5mA.