Session 15-4

A Programmable MEMS-Based Clock Generator
with Sub-ps Jitter Performance

 

Abstract

A MEMS-based clock generator achieves sub-ps jitter in 0.18µm CMOS. Key enabling techniques include a 48MHz MEMS oscillator, a reference doubler, a linear XOR-based PFD, a switched-resistor loop filter using accumulation mode NMOS varactors, and native NMOS devices with an RC filter. The overall output at 156.25MHz achieves an integrated phase jitter of 668fs rms over an integration bandwidth of 10kHz-20MHz.