Session 18-1

A 27% Active-Power-Reduced 40-nm CMOS Multimedia
SoC with Adaptive Voltage Scaling
using Distributed Universal Delay Lines

 

Abstract

AVS technique for extremely scaled SoCs has been developed. To reduce design cost, we have developed a supply voltage control scheme employing universal delay line (UDL) for monitoring the critical path delay (TCRIT). The error to TCRIT is as small as that with replica delay line. The UDL can be used in any product without any need for customizing. We have shown that 40-nm CMOS SoCs using our AVS can reduce active power by 27%.