Session 20-1

A 20-Gb/s, 0.66-pJ/bit Serial Receiver
with 2-Stage Continuous-Time Linear Equalizer
and 1-Tap Decision Feedback Equalizer in 45nm SOI CMOS

 

Abstract

A power-efficient equalizing serial receiver, including a 2-stage continuous-time linear equalizer (CTLE) and 1-tap decision feedback equalizer (DFE), is reported operating at data rates of up to 20 Gb/s. The DFE adopts a half-rate speculative architecture without explicit summing amplifiers by injecting offset-controlling currents directly into StrongARM sampling latches. At 20 Gb/s, a PCB trace with 26.3dB of loss is equalized while consuming 13.2mW (0.66 pJ/bit).