Session 20-2

A 40Gb/s Adaptive Receiver with Linear Equalizer
and Merged DFE/CDR

 

Abstract

A 40Gb/s adaptive receiver using a linear equalizer and a merged half-rate DFE/CDR circuit is fabricated in a 65nm process. For a 40Gb/s PRBS of 27-1, the measured jitter of the retimed data is 9.8pspp and 10.7pspp with BER<10-12 for the channel loss of 6.7dB and 23.5dB, respectively.