Session 21-2

On-chip Combined C-V/I-V Transistor Characterization System
in 45-nm CMOS

 

Abstract

An on-chip transistor characterization system for combined C-V/I-V characterization is presented. Capacitance measurement uses a quasi-static charged-based measurement technique with atto-Farad resolution. Random and systematic variability in device I-V and C-V characteristics is studied. The random variability in intrinsic gate capacitance is shown to exhibit Pelgrom scaling. Correlation between I-V and C-V measurements is used to identify systematic channel-length variation gradients in a device array.