Session 22-1

3D Stackable 32nm High-K/Metal Gate SOI
Embedded DRAM Prototype

 

Abstract

For the first time we report a high performance embedded DRAM prototype fabricated in a 3D stackable 32nm High-K/Metal Gate technology with copper through-silicon vias. Post through-via processing functional test demonstrates that <1.5ns latency and 500MHz operation are preserved.