Session 22-2

In-substrate-bitline Sense Amplifier
with Array-noise-gating Scheme
for Low-noise 4F² DRAM Array Operable at 10-fF Cell Capacitance

 

Abstract

An in-substrate-bitline sense amplifier (SA) with an array-noise-gating (ANG) scheme-for stable sensing operation in a 4F2 DRAM array with cell capacitance of under 20 fF-is proposed. A circuit simulation assuming 40-nm-class 4F2 DRAM chip shows that the SA reduces noise by 58% compared to a conventional SA and achieves stable sensing operation even at cell capacitance of 10 fF.