Session 24-1

A 45nm 48-core IA processor with Variation-Aware Scheduling
and Optimal Core Mapping

 

Abstract

This paper describes energy benefits of variation-aware dynamic voltage frequency scaling (VA-DVFS) schemes & presents measured WID Fmax, leakage & thermal variations for a 45nm 48-core IA processor. Measurements on a real system show that the proposed VA-DVFS & optimal core mapping schemes (VA-L & VA-LV) improve core computation energy by up to 21% & chip energy by up to 14.5% across varying voltage/frequency (V/F) operating points & core counts.