Session 26-1

Dual-Loop System of Distributed Microregulators
with High DC Accuracy, Load Response Time Below 500ps,
and 85mV Dropout Voltage

 

Abstract

A dual-loop architecture employs 8 distributed microregulators (UREGs) to achieve response times below 500ps in 45nm SOI CMOS. The trip point of a comparator inside each UREG is tuned for high DC accuracy with a local charge pump, which receives UP/DOWN currents from an outer feedback loop. Measured DC load regulation is better than 10mV down to an 85mV dropout voltage, and jitter readings in a CMOS delay line application indicate output noise below 28mVpp.