Session 4-1
A 12-ENOB 6X-OSR Noise-Shaped Pipelined ADC
Utilizing a 9-bit Linear Front-End
Abstract
| A noise-shaped pipelined ADC is presented in this paper. A minimal complexity Delta-Sigma modulator in the first two sub-ADCs and residue feedback in the latter stages lead to high-order noise shaping. This also leads to reduced sensitivity to analog imperfections in the front-end stage. Implemented in 0.18um CMOS, the ADC achieves 12~ENOB with 64MHz clock at 6XOSR. |