Session 4-3

A Continuous-Time, Jitter Insensitive Sigma Delta Modulator
using a Digitally Linearized G_m-C Integrator
with Embedded SC Feedback DAC

 

Abstract

This paper explores the use of a digitally linearized, low-power Gm-C integrator in the first stage of a 5th order CT sigma-delta modulator. The proposed architecture features a jitter insensitive SC feedback and a noisy-but-linear auxiliary modulator to estimate the nonlinearities of the first integrator in the main signal path. A 65-nm CMOS experimental prototype achieves 79 dB DR, and 73.3 dB peak SNDR for bandwidth of 1.95 MHz consuming 8.55 mW.