Session 6-3

A 7.2-GSa/s, 14-bit or 12-GSa/s, 12-bit DAC
in a 165-GHz f_T BiCMOS Process

 

Abstract

We describe a DAC which can operate at up to 7.2 GSa/s with 14-bit resolution or up to 12 GSa/s with 12-bit resolution. It uses a segmented architecture, with an R/2R ladder for the 10 LSBs; distributed resampling is applied to all current sources. The DAC achieves an SFDR of 77 dB at low output frequencies and an SFDR of 67 dB and an SNR of 62 dB from DC to 3 GHz. It demonstrates a phase noise of -157 dBc/Hz at 10 kHz from a 1 GHz carrier, 22 dB better than synthesized signal generation instruments.The DAC is built in a 165-GHz fT, 130-nm BiCMOS process and packaged in a 780-ball BGA.