Session 6-4

A 3GS/s, 9b, 1.2V single supply, pure binary DAC
with >50dB SFDR up to 1.5GHz in 65nm CMOS

 

Abstract

A 9b 3GS/s pure binary current steering DAC is implemented in 65nm CMOS. It demonstrates a low noise CML latch and a low power delay balancing technique while drawing 50mA from a single 1.2V power supply. When sampling at 3GHz, it exhibits more than 50dB SFDR until 1.5GHz output frequency and less than -60dB IM3 up to 1GHz output frequency. Total silicon area is less than 0.04mm2.