Session 7-2

A 40-nm 0.5-V 20.1-µW/MHz 8T SRAM
with Low-Energy Disturb Mitigation Scheme

 

Abstract

This paper presents a novel disturb mitigation scheme which achieves low-power and low-voltage operation for a deep sub-micron SRAM macro. We fabricated a 512-Kb 8T SRAM test chip that operates at a single 0.5-V supply voltage. The proposed scheme achieves 8.8-µW/MHz active energy in a write cycle and 72.8-µW leakage power, which are 35% and 26% better than the conventional write-back scheme. The total energy is 20.1 µW/MHz at 0.5 V.