Session 7-4

A Chip-ID Generating Circuit for Dependable LSI
using Random Address Errors on Embedded SRAM
and On-Chip Memory BIST

 

Abstract

A chip-ID generating scheme with high-tamper resistance is proposed. This enables to extract a unique finger print from each chip by using random failure bits in an SRAM under the ID generation mode, and on-chip memory BIST. The stability and average of Humming distance of 128 bit ID become 99.9999999% and 63.9, respectively. The proposed scheme does not require any additional hardware IPs.