Session 12-2

Variability and technology aware SRAM Product
yield maximization

 

Abstract

This work assesses the impact of process variability such as device mismatch of two in-house FinFET and a planar technology on key figures of merit (SNM and WTP) of SRAMs- for the first time not only at cell but also at product level. Statistical VCCmin analysis shows that VCC limits for array sizes are 512Kbit at 1V for planar, 2Mbit at 0.9V FOR BFF, and - far ahead - at least 1GBit at 0.7V for undoped SOIFF devices.