Session 2A-1

Scaling of SOI FinFETs down to Fin Width of 4 nm
for the 10nm technology node

 

Abstract

Using a novel structure, we fabricate SOI FinFETs with fin width of 4nm, fin pitch of 40nm, gate length of 20nm. We achieve robust yield on arrays of thousands of fins with high structural integrity. We experimentally observe Dfin-dependent performance degradation, increased variability, and VT shift. Capacitance measurements exhibit quantum confinement behavior which has been predicted to pose a fundamental limit to scaling FinFETs below 10nm LG.