Session 2A-2

Sub-25nm FinFET with Advanced Fin Formation
and Short Channel Effect Engineering

 

Abstract

FinFET devices achieving N/P Ion values of 1250/950 µA/µm at 100nA/µm at 1V, 1300/1000 µA/µm with self-heating correction, are demonstrated, using a dual work function gate-first process flow at 100 nm gate pitch and 40 nm fin pitch. Ring-oscillator (RO, FO=3) functionality has been demonstrated, showing excellent Vdd scalability. We have also demonstrated logic scan chain functionality and yield improvement by optimizing the gate stack process. An optimized SIT process has been developed to improve short-channel characteristics in devices with a small number of fins in a narrow active area, which is also critical for manufacturability improvement. Various conformal doping techniques for NFET/PFET are optimized to improve device performance.