Session 3A-5

RF and Mixed-Signal Performances
of a Low Cost 28nm Low-Power CMOS Technology
for Wireless System-on-Chip Applications
Abstract

Extending RF/MS-CMOS to 28nm low-power Poly/SiON node for the next generation wireless S°C applications makes most economic sense because, beyond 28nm, costly HiK/MG, double-patterning, complex local interconnect, and multi-gate structures will be required for more Moore scaling. Competitive peak fT/Fmax of 349/265GHz for NMOS, 242/184GHz for PMOS, with excellent mixed-signal properties, are reported. Effects associated with layout dependency, poly pitch, and DFM-related rules, are shown to degrade fT by ~10%, thus, require careful optimization