Session 4A-5

A 0.021 μm2 trigate SRAM Cell
with Aggressively Scaled Gate and Contact Pitch

 

Abstract

We present the highest density demonstration of CMOS technology reported to date featuring a 6T SRAM cell size of 0.021 um2. The motivation for this work was to explore the limits of device patterning and basic module integration at dimensions relevant to the 10 nm node. A trigate device architecture with a minimum contacted gate pitch and minimum contacted fin pitch of 50 nm was used as the target technology for this demonstration.