Session 5A-4
An Efficient Manufacturing Technique based
on Process Compact Model to Reduce Characteristic Variation
beyond Process Limit for 40nm Node Mass Production
| Practical manufacturing technique to reduce characteristic variation of 40nm CMOS device has been developed. Novel feed-forward (FF) system at gate formation for tight gate length control, and FF techniques at both halo implantation and Spike RTA for device centering have been applied. In addition, adjusting wafer notch angle at each critical process step has been utilized to suppress within-wafer variation. As a result, total Vth variation at mass production has been reduced by 46%. |